Memory Cache Control Functions
Memory cache control functions perform a cache control or mode setting.
The approach of cache control in μT-Kernel is as follows:
Basically, even if application and device driver programs are created without paying attention to the existence of cache, the appropriate cache control should be automatically performed during their execution. Especially, in consideration of program portability, functions with strong dependency on system including cache are better to be handled separately from application programs wherever possible. For this reason, it is the policy of individual systems based on μT-Kernel to make the μT-Kernel itself control the cache automatically.
Specifically, μT-Kernel sets the cache so that it is turned ON for space like memory to store usual programs or data, and OFF for space such as I/O. For this reason, ordinary application programs do not need to explicitly call a function for cache control. Appropriate cache control is automatically performed even if cache control is not explicitly performed from the program.
However, the cache control by μT-Kernel only (cache control by default setting) may not be enough for particular situations. For example, for I/O processing with DMA transfer or using memory space outside the kernel management, explicit cache control may be required. When executing a program by dynamically loading or generating (compiling) it, such cache control may be required so that data cache and instruction cache are appropriately synchronized. Memory cache control functions are assumed to be used in these situations.
 | Difference from μT-Kernel 1.0 |
|---|---|
New function introduced based on T-Kernel 2.0 specification. |
SetCacheMode - Set Cache Mode
Related Service Profile Items
| TK_SUPPORT_WBCACHE | Support for specifying write-back mode for cache mode(CM_WB) |
| TK_SUPPORT_WTCACHE | Support for specifying write-through mode for cache mode(CM_WT) |
Only when all the service profile items below are set to be effective, this system call can be used.
Description
Sets the cache mode for a memory area. Specifically, performs the setting specified in mode for the cache of the len bytes memory area from the address addr. The memory cache mode is set in page units.
mode := ( CM_OFF || CM_WB || CM_WT ) | [CM_CONT]
CM_OFF Cache off
CM_WB Cache on (write back)
CM_WT Cache on (write through)
CM_CONT Applies the cache setting only for the contiguous physical address space
...
/* Implementation-dependent mode may be added */
Specify CM_OFF in mode to flush (writes back) the cache, invalidate it, and turn it off.
Specify CM_WT in mode to flush the cache and then set the write through cache mode.
Specify CM_WB in mode to set the write back cache mode. In this case, whether or not to flush the cache is implementation-dependent.
If mode is specified by CM_CONT, only the physically consecutive region starting at addr becomes the target of the cache mode setting. If the corresponding physical addresses are not contiguous within the specified virtual address region, or if there are paged-out regions, the processing stops at the first such non-contiguous region or paged-out region, and the length of the region to which the mode setting is done is returned. If CM_CONT is not specified, then the all area is the target of the cache mode processing, and the size of the area for which the processing has been performed is returned.
Some or all of the cache mode settings may be unusable depending on CPU or implementation. If an unusable mode is specified, E_NOSPT is returned without any processing.
len must be 1 or more. If a value of 0 or less is specified, the error code E_PAR is returned.
Additional Notes
Because the cache mode setting is performed in page units, the start address of the page including addr and subsequent addresses is taken as the setting target when addr is not on the page border. Note that unintended cache access may occur to adjacent area when using this API. The page size is implementation-dependent and can be obtained using GetSpaceInfo.
When you want more detailed cache mode settings depending on the hardware configuration or the cache function of CPU, add and use an implementation-dependent mode. For example, NORMAL CACHE OFF (Weakly Order), DEVICE CACHE OFF (Weakly Order), STRONG ORDER, or other cache mode may be specified.
When an unavailable mode is specified, it is implementation-dependent whether to generate an error as E_NOSPT or E_PAR.
Difference from T-Kernel 2.0
The data type of parameter len and return parameter rlen has been changed from INT to SZ.
Difference from μT-Kernel 1.0
New API introduced based on T-Kernel 2.0 specification
ControlCache - Control Cache
Related Service Profile Items
Only when all the service profile items below are set to be effective, this system call can be used.
Description
Control the cache (flush or invalidate) of a memory area. Specifically, performs the control specified in mode for the cache of the len bytes memory area from the logical address addr.
mode := (CC_FLUSH | CC_INVALIDATE)
CC_FLUSH Flush (write back) cache
CC_INVALIDATE Invalidate cache
...
/* Implementation-dependent mode values may be added */Both CC_FLUSH and CC_INVALIDATE can be set at the same time. This combination flushes the cache and then invalidates it.
If the processing is successful, the size of the processed space is returned. If a paged out area exists within the specified space, the processing is aborted immediately before it and the size of the processed space is returned.
A range that spans areas with different cache modes or attributes must not be specified. For example, a range that spans areas with cache on and cache off, task space and task shared space, or areas with different protection levels must not be specified. If such a range is specified, the subsequent correct behavior is not guaranteed.
The detail of the function varies depending on CPU, hardware, or implementation because the cache control depends heavily on the hardware. The cache control is basically applied on the specified area using the specified mode, but it may affect more area including the specified area. For example, there are the following cases:
Only the exactly specified range is not always controlled (flushed or invalidated). An area including the specified range is controlled, but it is also possible to flush or invalidate the cache for other areas (for example, entire memory) depending on CPU, hardware, or implementation.
Normally, no operation is performed when a cache-off area is specified. Even in this case, it is possible to flush or invalidate the cache for areas other than the specified range.(always flush the entire space, etc.)
No operation is performed in a system without cache.
Generally, the cache control is performed in cache line size units. For this reason, note that unintended cache access may occur to adjacent area when using this API. The cache line size is implementation-dependent and can be obtained using GetSpaceInfo.
Difference from T-Kernel 2.0
The data type of parameter len and return parameter rlen has been changed from INT to SZ.
Difference from μT-Kernel 1.0
New API introduced based on T-Kernel 2.0 specification