- K. Sakamura. Development of TRON Chip: a Single Chip VLSI Computer
Architecture in the 1990's. In Proceedings of IFIP TC 10/WG 10.5
International Conference on Very Large Scale Integration (1985),
IFIP, pp. 115-124.
- T. Enomoto. M32: Mitsubishi 32-bit Microprocessor Based on TRON
CPU Specification. In Proceedings of the Second TRON Project Symposium
(Mar. 1987), TRON Association, pp. 40-47. in Japanese.
- J. J. Farrell III. The CPU to System Connection. In TRON Project
1987 (1987), Springer-Verlag, pp. 18-25.
- H. Inayoshi, and M. Itoh. Development of HF32 Family VLSI Processor.
In Proceedings of the Second TRON Project Symposium (Mar. 1987),
TRON Association, pp. 56-70. in Japanese.
- M. Itoh. Architecture Characteristics of Gmicro/300. In TRON
Project 1987 (1987), Springer-Verlag, pp. 273-280.
- M. Kainaga, T. Nojiri, and T. Kawasaki. A Study of High Level
Language Based Machine Description Language. In Proceedings of
the Second Realtime-OS-TRON Technical Workshop (Jul. 1987), IEICE,
pp. 2-12. in Japanese.
- S. Kamiya. Toshiba VLSI CPU Based on TRON CPU Specification.
In Proceedings of the Second TRON Project Symposium (Mar. 1987),
TRON Association, pp. 48-55. in Japanese.
- T. Kiyohara, M. Deguchi, and T. Sakao. Implementation Methods
of CPU's Based on TRON CPU Specification. In Proceedings of the
Second TRON Project Symposium (Mar. 1987), TRON Association, pp.
34-39. in Japanese.
- T. Kiyohara, M. Deguchi, and T. Sakao. Pipeline Structure of
Matsushita 32-bit Microprocessor. In TRON Project 1987 (1987),
Springer-Verlag, pp. 281-289.
- M. Miyata, Y. Masubuchi, and H. Kishigami. Design of TX1 Pipeline
Structure. In Proceedings of the Second Realtime-OS-TRON Technical
Workshop (Jul. 1987), IEICE, pp. 13-22. in Japanese.
- K. Namimoto, T. Satoh, and A. Kanuma. TX Series Based on TRONCHIP
Architecture. In TRON Project 1987 (1987), Springer-Verlag, pp.
291-308.
- Y. Nozuyama, A. Nishimura, and J. Iwamura. Testability Design
of High-Performance 32bit-Microprocessor TX1. In Proceedings of
the National Convention of IEICE: Semiconductor and Device (1987),
pp. 1-124. in Japanese.
- K. Sakamura. Architecture of the TRON VLSI CPU. IEEE Micro,
Vol. 7, No. 2 (Apr. 1987), pp. 17-31.
- K. Sakamura. Architecture of VLSI CPU in the TRON Project. In
Proceedings of the Second TRON Project Symposium (Mar. 1987),
TRON Association, pp. 1-33.
- K. Sakamura. Instruction Format of TRON VLSI CPU. In Proceedings
of the Third Realtime-Architecture-TRON Technical Workshop (Oct.
1987), IEICE, pp. 8-39. in Japanese.
- K. Sakamura. TRON VLSI CPU: Concepts and Architecture. In TRON
Project 1987 (1987), Springer-Verlag, pp. 199-238.
- A. J. Smith. Design Considerations for TRON Cache Memories.
In TRON Project 1987 (1987), Springer-Verlag, pp. 239-247.
- K. Takagi, T. Nishimukai, K. Iwasaki, I. Kawasaki, and H. Inayoshi.
Outline of Gmicro/200 and Memory Management Mechanism. In TRON
Project 1987 (1987), Springer-Verlag, pp. 259-272.
- O. Tomisawa, T. Yoshida, M. Matsuo, T. Shimizu, and T. Enomoto.
Design Considerations of the Gmicro/100. In TRON Project 1987
(1987), Springer-Verlag, pp. 249-258.
- T. Yoshida, M. Matsuo, T. Ueda, and T. Shimizu. Branch Prediction
in a Pipelined Microprocessor. IPSJ SIG Notes on Microcomputer,
44-1 (Mar. 1987), IPSJ. in Japanese.
- A. Bigazzi, J. E. Lillge, and D. E. Jaskolski. An Integrated
Software Development Toolkit for the Gmicro/200. In TRON Project
1988 (1988), Springer-Verlag, pp. 363-380.
- C. Hori, J. Iwamura, and M. Miyata. Design Methodology of TX1
Based on the TRON Architecture. IEICE SIG Reports, CPSY 88-58
(Dec. 1988), IEICE, pp. 9-13. in Japanese.
- H. Inayoshi, I. Kawasaki, T. Nishimukai, and K. Sakamura. Realization
of Gmicro/200. IEEE Micro, Vol. 8, No. 2 (Apr. 1988), pp. 12-21.
- S. Ishimaru, and K. Tamaru. Development Support System for TX
Series. In TRON Project 1988 (1988), Springer-Verlag, pp. 351-361.
- N. Itoh, H. Nojima, and Y. Mori. Architectural Features of OKI
32-Bit Microprocessor. In TRON Project 1988 (1988), Springer-Verlag,
pp. 247-262.
- J. Iwamura, H. Kishigami, A. Ishii, and K. Usami. Implementation
and Evaluation of the TRONCHIP Specification for the TX1. In TRON
Project 1988 (1988), Springer-Verlag, pp. 285-300.
- J. Iwamura, T. Tokumura, and K. Okamoto. 32-bit Microprocessor
Family Based on TRON Architecture, TX Series. TOSHIBA Review,
Vol. 43, No. 11 (1988), pp. 1-4. in Japanese.
- K. Iwasaki, H. Aoki, M. Hanawa, I. Kawasaki, T. Nakazawa, and
H. Inayoshi. A Consideration of 2-clock Bus Cycle Access for Gmicro/200
Microprocessor. In Proceedings of the Fall National Convention
of IEICE (1988), pp. c-2-92. in Japanese.
- Y. Kashiwagi, H. Chaki, and M. Narushima. Development of a C
Compiler for Gmicro Microprocessor Based on TRON Architecture.
In TRON Project 1988 (1988), Springer-Verlag, pp. 341-350.
- H. Kida, M. Watabe, T. Nakamikawa, S. Morinaga, S. Kawasaki,
and H. Inayoshi. A Floating Point Processing Unit for the Gmicro
CPU. In TRON Project 1988 (1988), Springer-Verlag, pp. 301-316.
- M. Kimura, T. Iwasaki, S. Mori, K. Fujita, and S. Hazama. A
40 MB/s 32 Bit DMA Controller with 3411 Product Terms PLA. In
TRON Project 1988 (1988), Springer-Verlag, pp. 332-339.
- H. Kishigami, Y. Masubuchi, T. Utsumi, T. Miyamori, and M. Miyata.
CPU Architecture of 32bit Microprocessor TX1 Based on TRONCHIP
Specification. IPSJ SIG Notes on Microcomputer, 48-9 (Jan. 1988),
IPSJ, pp. 65-72. in Japanese.
- T. Kitahara, M. Yuhara, A. Fujihira, M. Mitsuhashi, and M. Itoh.
High Performance Bus Interface of Gmicro/300. In TRON Project
1988 (1988), Springer-Verlag, pp. 317-329.
- T. Kiyohara, T. Sakao, K. Adachi, and O. Nishijima. Design Considerations
of the Matsushita 32-Bit Microprocessor for Real-Memory Systems.
In TRON Project 1988 (1988), Springer-Verlag, pp. 263-273.
- E. Masuda, and K. Okamoto. Design Methodology of the TRONCHIP
TX1. Proceedings of TRON Technical Workshop, Vol. 1, No. 2 (Oct.
1988), pp. 49-58. in Japanese.
- T. Matsuzaki, M. Deguchi, and T. Sakao. Parallel Variable-Length
Instruction Decoding. Proceedings of TRON Technical Workshop,
Vol. 1, No. 2 (Oct. 1988), pp. 33-36. in Japanese.
- T. Miyamori, H. Kishigami, and M. Miyata. The Characteristic
of TRONCHIP Instruction Set in the 32bit MPU TX1 System. IEICE
SIG Reports, CPSY 88-57 (Dec. 1988), IEICE, pp. 1-8. in Japanese.
- T. Miyamori, H. Kishigami, and M. Miyata. Considerations for
CPU Architecture of 32bit Microprocessor TX3 Based on TRONCHIP
Specification. IEICE SIG Reports, CPSY 87-53 (Mar. 1988), IEICE,
pp. 31-36. in Japanese.
- M. Miyata, H. Kishigami, K. Okamoto, and S. Kamiya. The TX1
32-Bit Microprocessor: Performance Analysis and Debugging Support.
IEEE Micro, Vol. 8, No. 2 (Apr. 1988), pp. 37-46.
- S. Narita, T. Okada, M. Hanawa, and T. Nishimukai. High-Speed
Branch Control Scheme for Microprogram-Controlled Microprocessor.
Proceedings of TRON Technical Workshop, Vol. 1, No. 2 (Oct. 1988),
pp. 37-48. in Japanese.
- Y. Nishikawa, M. Deguchi, and T. Sakao. An Examination of the
Fundamental Configuration of the Microprocessor for Virtual Memory
Systems. In TRON Project 1988 (1988), Springer-Verlag, pp. 275-283.
- T. Nishimukai, H. Inayoshi, K. Takagi, K. Iwasaki, I. Kawasaki,
M. Hanayama, and T. Okada. Cache-based Pipeline Architecture in
the Hitachi H32/200 32-bit Microprocessor. In Proceedings of the
International Conference on Computer Design (Rye Brook, NY, Oct.
1988), pp. 102-105.
- A. Nishimura, Y. Nozuyama, and J. Iwamura. Testability Design
of a 32bit Microprocessor TX1. IEICE SIG Reports, ICD 88-28 (Jun.
1988), IEICE, pp. 9-15. in Japanese.
- Y. Nozuyama, A. Nishimura, and J. Iwamura. Design for Testability
of a 32-bit Microprocessor, the TX1. In Proceedings of the International
Test Conference 1988 (Washington D. C., Sep. 1988), pp. 172-182.
- T. Okada, F. Arakawa, S. Narita, K. Iwasaki, K. Takagi, T. Nishimukai,
T. Kawasaki, and H. Inayoshi. Some Techniques to Improve Gmicro/200
Performance Utilizing Pipeline Processing. In Proceedings of the
Fourth Realtime-Architecture-TRON Technical Workshop (Feb. 1988),
IEICE, pp. 4-13. in Japanese.
- K. Okamoto, M. Miyata, H. Kishigami, T. Miyamori, and T. Sato.
Design Considerations for 32bit Microprocessor TX3. In Proceedings
of the 33rd IEEE Computer Society International Conference (1988),
IEEE Computer Society Press, pp. 25-29.
- Y. Saitoh, T. Yoshida, M. Matsuo, Y. Watanabe, and T. Shimizu.
Design of Pipeline Structure in a TRON Based Microprocessor Gmicro/100.
IEICE SIG Reports, CPSY 88-59 (Mar. 1988), IEICE. in Japanese.
- K. Sakamura, K. Kinbara, and Y. Tominaga. The TRON Project and
Development of a TRON-Spec 32-Bit Microprocessor. In Proceedings
of 1988 Symposium on VLSI Circuits (Tokyo, 1988), The Japan Society
of Applied Physics and the IEEE Solid-State Circuits Council in
Cooperation with the IEICE.
- K. Sakamura, R. Sano, and K. Honma. Introducing Tobus, the System
Bus in the TRON Architecture. IEEE Micro, Vol. 8, No. 2 (Apr.
1988), pp. 47-59.
- T. Shimizu, T. Yoshida, Y. Saito, M. Matsuo, and T. Enomoto.
A 32bit Microprocessor Based on the TRON Architecture: Design
of the Gmicro/100. In Proceedings of the 33rd IEEE Computer Society
International Conference (1988), IEEE Computer Society Press,
pp. 30-33.
- K. Tamaru, S. Kamiya, and M. Miyata. Development Support System
for TRON TX Series. TOSHIBA Review, Vol. 43, No. 11 (1988), pp.
905-908. in Japanese.
- O. Tomisawa, N. Yamada, K. Saito, and S. Ishiyama. VLSI Microprocessor.
Technical Reviews of Mitsubishi Electric, Vol. 62, No. 8 (1988),
pp. 657-660.
- M. Tonomura, I. Kawasaki, H. Inayoshi, and K. Hashimoto. Common
Controlling Method for Microprogram. In Proceedings of the Fall
National Convention of IEICE (1988), pp. C-2-92. in Japanese.
- T. Yaguchi, K. Tanaka, K. Tamaru, and A. Kanuma. Performance
Analysis of Token Ring LAN Processor TRL1 Which Super-integrates
the 32bit TRONCHIP TX1. In Proceedings of the Fourth Realtime-Architecture-TRON
Technical Workshop (Feb. 1988), IEICE, pp. 14-25. in Japanese.
- T. Yoshida, Y. Saitoh, M. Matsuo, and T. Shimizu. The Pipelining
Mechanism of a TRON Based Microprocessor Gmicro/100. IEICE SIG
Reports, CPSY 87-52 (Mar. 1988), IEICE. in Japanese.
- D. Agarwal, F. Wang, and M. Ghiassi. Generation and Debugging
of Optimized Code for the TRON Architecture. In TRON Project 1989
(1989), Springer-Verlag, pp. 297-320.
- F. Arakawa, K. Iwasaki, N. Yamaguchi, and M. Hanawa. Proposal
of Design for Testability of VLSI Processors and Its Application
to Gmicro/200. Proceedings of TRON Technical Workshop, Vol. 2,
No. 2 (Jul. 1989), pp. 27-38. in Japanese.
- Y. Asao, T. Yoshida, and K. Tamaru. Designs for a Single Board
Computer with the TRON Specification Microprocessor TX1. Proceedings
of TRON Technical Workshop, Vol. 2, No. 2 (Jul. 1989), pp. 1-9.
in Japanese.
- C. Franklin, and M. Haden. Advanced Optimizing Compilers Boost
Performance on TRON Specification Chip Pipelined CISC Architectures.
In TRON Project 1989 (1989), Springer-Verlag, pp. 253-270.
- K. Hashimoto, M. Kubo, A. Hasegawa, S. Yoshioka, S. Matsui,
and M. Tonomura. Microprogram Evaluation Scheme for Gmicro/200.
Proceedings of TRON Technical Workshop, Vol. 2, No. 1 (Apr. 1989),
pp. 1-10. in Japanese.
- J. Hinata, T. Yoshida, Y. Saito, A. Ohtsuka, T. Shimizu, and
O. Tomisawa. Implementation and Performance Evaluation of the
M32/100. In TRON Project 1989 (1989), Springer-Verlag, pp. 285-295.
- J. Hinata, S. Ishiyama, T. Yoshida, O. Tomisawa, and J. Korematsu.
TRON Specification 32-bit Microprocessor M32/100. Technical Reviews
of Mitsubishi Electric, Vol. 63, No. 11 (1989), pp. 921-924.
- A. Ishii, H. Kishigami, K. Usami, and J. Iwamura. Implementation
and Evaluation of the TRON Specification for the TX1. IEICE SIG
Reports, ICD 89-13 (Apr. 1989), IEICE, pp. 37-42. in Japanese.
- J. Iwamura, C. Hori, and M. Miyata. Design Methodology of a
VLSI Processor Based on the TRON Architecture. In Design Methodologies
for VLSI and Computer Architecture (1989), pp. 341-345.
- S. Iwata, T. Shimizu, M. Matsuo, T. Yoshida, J. Hinata, and
O. Tomisawa. Implementation of a 32-bit Microprocessor Gmicro/100
Based on TRON Specification: (1) Implementation and Evaluation
of Microprogram. In Proceedings of the 38 th National Convention
IPSJ (1989), IPSJ. in Japanese.
- R. Kato, T. Miyamori, S. Hayashida, and M. Miyata. Performance
Evaluation of 32-bit Microprocessor TX1. In Proceedings of the
39th National Convention IPSJ (1989), IPSJ, pp. 1816-1817. in
Japanese.
- S. Katsunori, T. Shimizu, S. Iwata, T. Yoshida, J. Hinata, and
O. Tomisawa. Implementation of a 32-bit Microprocessor Gmicro/100
Based on TRON Specification: (3) Microprogramming Support System
on the Relational Database. In Proceedings of the 38 th National
Convention IPSJ (1989), IPSJ. in Japanese.
- S. Kawasaki, M. Watabe, and S. Morinaga. A Floating Point VLSI
Chip for the TRON Architecture: An Architecture for Reliable Numerical
Programming. IEEE Micro, Vol. 9, No. 3 (Jun. 1989), pp. 26-44.
- K. Kimura, T. Kiyohara, M. Deguchi, and T. Sakao. Instruction
Decoding Method for a 32-Bit Microprocessor Based on TRON Specification.
Proceedings of TRON Technical Workshop, Vol. 2, No. 3 (Oct. 1989),
pp. 11-18. in Japanese.
- H. Kishigami, and T. Miyamori. Performance Analysis of TRON
32-bit TX1 Microprocessor. TOSHIBA Review, Vol. 44, No. 7 (1989),
pp. 566-569. in Japanese.
- H. Kishigami, T. Miyamori, and M. Miyata. The Effectiveness
of TRONCHIP Instructions in the TX1 System. In Proceedings of
the 34th IEEE Computer Society International Conference -- COMPCON
Spring 1989 (1989), IEEE Computer Society Press, pp. 43-47.
- T. Kitahara, T. Satoh, T. Ohshima, and A. Yoshitake. Pipeline
Structure of Gmicro/300 32bit Microprocessor. Proceedings of TRON
Technical Workshop, Vol. 2, No. 3 (Oct. 1989), pp. 1-10. in Japanese.
- M. Matsuo, T. Ueda, T. Yoshida, and Y. Saitoh. The Instruction
Pipeline Used for the TRON Based 32-bit Microprocessor M32/100
and Its Performance Evaluation. IEICE SIG Reports, ICD 89-161
(Nov. 1989), IEICE. in Japanese.
- T. Miyamori, T. Yoshida, and H. Kishigami. Design of Microcomputer
Systems Using the TX1 Family LSIs. In TRON Project 1989 (1989),
Springer-Verlag, pp. 271-284.
- T. Nakano, Y. Saitoh, M. Matsuo, T. Ueda, Y. Watanabe, T. Yoshida,
S. Iwata, S. Kobayashi, T. Shimizu, and J. Hinata. The Logic Verification
Method Applied to a TRON Based Microprocessor Gmicro/100. IEICE
SIG Reports, CAS 89-8 (Jun. 1989), IEICE. in Japanese.
- A. Nishimura, Y. Nozuyama, and J. Iwamura. Design for Testability
of a 32Bit Microprocessor TX1 and Its Application to the Evaluation
and Debugging. Transactions of IEICE, Vol. J72-C-II, No. 5 (May
1989), pp. 449-455. in Japanese.
- Y. Nozuyama, A. Nishimura, and J. Iwamura. Implementation and
Evaluation of Microinstruction Controlled Self Test Using a Masked
Microinstruction Scheme. In Proceedings of the International Test
Conference 1989 (Washington D. C., Aug. 1989), pp. 624-632.
- A. Ohtsuka, S. Kobayashi, F. Kitamura, Y. Kittaka, T. Yoshida,
and J. Hinata. The Bus-Interface in M32/100. Proceedings of TRON
Technical Workshop, Vol. 2, No. 2 (Jul. 1989), pp. 11-25. in Japanese.
- K. Okamoto, H. Kishigami, and T. Miyamori. The Characteristic
and Effectiveness of TX1 Instructions Based on TRON Specification.
Proceedings of TRON Technical Workshop, Vol. 2, No. 1 (Apr. 1989),
pp. 53-64. in Japanese.
- K. Sakamura, and T. Enomoto. 32-bit Microprocessors Based on
the TRON Specification. Microprocessors and Microsystems, Vol.
13, No. 8 (Oct. 1989), pp. 503-513.
- K. Sakamura, and T. Enomoto. 32-bit Microprocessors Based on
the TRON Specification. Journal of Information Processing Society
of Japan, Vol. 30, No. 5 (May 1989), pp. 565-573. in Japanese.
- T. Shimizu, S. Iwata, Y. Saito, T. Yoshida, M. Matsuo, J. Hinata,
and K. Saito. A 32-bit Microprocessor with High Performance Bit-map
Manipulation Instructions. In Proceedings of the 1989 International
Conference on Computer Design: VLSI in Computers and Processors
(Cambridge, MA, Oct. 1989), pp. 406-409.
- M. Suzuki, Y. Nishikawa, M. Deguchi, and T. Sakao. The Microprogram
Verification of a 32-Bit Microprocessor MN10400 Based on TRON
Specification. IEICE SIG Reports, ICD 89-162 (Nov. 1989), IEICE.
in Japanese.
- T. Takahashi, N. Ito, T. Hoshino, Y. Watanabe, K. Sakamura,
H. Takada, H. Nakamura, and N. Nishio. Development of a Parallel
Computer System Using TRON Chip and Its Application to Physics.
Proceedings of TRON Technical Workshop, Vol. 2, No. 1 (Apr. 1989),
pp. 21-30. in Japanese.
- T. Tokumura, E. Masuda, C. Hori, K. Usami, M. Miyata, and J.
Iwamura. Design of a 32-bit Microprocessor, TX1. IEEE Journal
of Solid-State Circuits, Vol. 24, No. 4 (Aug. 1989), pp. 938-944.
- Y. Toshiya, Y. Asao, K. Chiba, and N. Handa. TRON 32-bit TX1
Single-board Computer. TOSHIBA Review, Vol. 44, No. 7 (1989),
pp. 570-573. in Japanese.
- K. Usami, and J. Iwamura. Optimized Design Method for Full-Custom
Microprocessors. In Proceedings of the IEEE 1989 Custom Integrated
Circuits Conference (San Diego, CA, May 1989), pp. 19.5.1-19.5.5.
- K. Usami, and J. Iwamura. Optimized Design Method for Full-Custom
Microprocessors. IPSJ SIG Notes on Design Automation, 47-1 (May
1989), IPSJ. in Japanese.
- Y. Watanabe, T. Shimizu, S. Iwata, Y. Saito, T. Yoshida, and
O. Tomisawa. Implementation of a 32-bit Microprocessor Gmicro/100
Based on TRON Specification: (2) Management of Microprogram and
Design of Microdecoder by Relational Database. In Proceedings
of the 38 th National Convention IPSJ (1989), IPSJ. in Japanese.
- C. Franklin, and C. Rosenberg. Inline Procedures Boost Performance
on TRON Architecture. In TRON Project 1990 (1990), Springer-Verlag,
pp. 275-292.
- S. Fukuda, and M. Itoh. Introduction and Features of TOXBUS
(TRON-Specification Bus). Proceedings of TRON Technical Workshop,
Vol. 3, No. 1 (Jun. 1990), pp. 65-78. in Japanese.
- K. Kimura, T. Kiyohara, and M. Deguchi. Instruction Decoder
Applied to Variable-Length Instruction. IEICE SIG Report, CPSY
90-86 (Nov. 1990), IEICE. in Japanese.
- Y. Kimura, H. Shida, S. Sasaki, and H. Ito. SRM32: Implementation
of Symbolic ROM Monitor on Gmicro F32 Series. In TRON Project
1990 (1990), Springer-Verlag, pp. 325-345.
- T. Kitahara, and T. Satoh. The Gmicro/300 32-bit Microprocessor.
IEEE Micro, Vol. 10, No. 3 (Jun. 1990), pp. 68-75.
- T. Kitahara, T. Satoh, T. Ohshima, and A. Fujihira. Performance
Evaluations of TRON Based 32-bit Microprocessor Gmicro/300. IEICE
SIG Report, ICD 90-5 (1990), IEICE.
- T. Kiyohara, M. Deguchi, T. Sakao, K. Adachi, O. Nishijima,
S. Araki, E. Tadamatsu, H. Miyazaki, and T. Sakurai. 32-Bit Microprocessor
MN10400. National Technical Report, Vol. 36, No. 3 (Jun. 1990),
pp. 63-70.
- T. Kiyohara, and K. Adachi. 32 Bit Microprocessor MN10400. Proceedings
of TRON Technical Workshop, Vol. 2, No. 4 (Feb. 1990), pp. 57-63.
in Japanese.
- M. Miyazaki, T. Kiyohara, T. Watanabe, M. Deguchi, and T. Sakao.
The Pipleline Control System and Verification Method of a 32-bit
Microprocessor MN10400 Based on TRON Specification. IEICE SIG
Reports, ICD 90-3 (Apr. 1990), IEICE. in Japanese.
- M. Miyazaki, T. Kiyohara, T. Watanabe, M. Deguchi, and T. Sakao.
The Pipeline Control System and Verification Method of a 32-bit
Microprocessor MN10400 Based on TRON Specification. IEICE SIG
Report, ICD 90-3 (1990), IEICE.
- Y. Mori, Y. Haneda, Y. Arakawa, T. Mori, and M. Kumazawa. Implementation
and Evaluation of Oki 32-bit Microprocessor O32. In TRON Project
1990 (1990), Springer-Verlag, pp. 221-234.
- H. Nakagawa, A. Yamada, M. Hata, T. Hiraki, K. Nishida, J. Korematsu,
K. Sawai, I. Ishida, T. Watanabe, and A. Ohsaki. The Configuration
of Cache Controller/Memory (CCM) for the GmicroFamily Microprocessors.
Proceedings of TRON Technical Workshop, Vol. 3, No. 1 (Jun. 1990),
pp. 29-38. in Japanese.
- Y. Nakao, M. Ohki, and N. Kitakami. A Development of ASSP with
M32/100 MPU Core Based on TRON Specifications. IPSJ SIG Notes
on Microcomputer and Workstation, 62-4 (Jun. 1990). in Japanese,MIC
62-4.
- S. Narita, F. Arakawa, T. Okada, and K. Uchiyama. Parallel Instruction
Decoding for Variable Length Instruction Set. In Proceedings of
the Fall National Convention of IEICE (1990), pp. 6-78. in Japanese.
- H. Neugass. A Forth Kernel for Gmicro. In TRON Project 1990
(1990), Springer-Verlag, pp. 293-310.
- Y. Nozuyama. Realization of an Efficient Design Verification
Test Based on a Microinstruction Controlled Self Test. In Proceedings
of the International Test Conference 1990 (Washington D. C., Sep.
1990), pp. 327-336.
- A. Ohtsuka, Y. Saitoh, F. Itomitsu, , S. Iwata, and T. Yoshida.
Testability Features of the 32-bit Microprocessor M32/10. IEICE
SIG Reports, ICD 90-4 (Apr. 1990), IEICE. in Japanese.
- K. Okada, M. Itoh, S. Fukuda, T. Hirosawa, T. Utsumi, K. Yoshioka,
Y. Tanigawa, and K. Hirano. Performance Evaluation of TOXBUS.
In TRON Project 1990 (1990), Springer-Verlag, pp. 347-374.
- C. Reiher, and W. P. Taylor. The Gmicro Microprocessor and the
AT&T UNIX Operating System. In TRON Project 1990 (1990), Springer-Verlag,
pp. 311-324.
- M. Sakamoto, T. Shimizu, and K. Saitoh. The Design of M32/100's
Bitmap Instructions Used in the Graphic Primitive. In TRON Project
1990 (1990), Springer-Verlag, pp. 261-271.
- K. Sakamura, and T. Enomoto. 32-Bit Microprocessors Based on
the TRON Architecture Specification. Transactions of Information
Processing Society of Japan, Vol. 30, No. 5 (Feb. 1990), pp. 565-573.
in Japanese.
- M. Suzuki, T. Kiyohara, and M. Deguchi. Design Considerations
of On-Chip-Type Floating-Point Units. In TRON Project 1990 (1990),
Springer-Verlag, pp. 235-248. T. Ueda, M. Matsuo, S. Iwata, and
T. Yoshida. The Functional Simulator of the TRON Based 32-bit
Microprocessor M32/100. IEICE SIG Report, VLD 89-111,ICD 89-199
(1990), IEICE.
- T. Ueda, M. Matsuo, S. Iwata, and T. Yoshida. The Functional
Simulator of the TRON Based 32-bit Microprocessor M32/100. IEICE
SIG Reports, VLD 89-111 (Mar. 1990), IEICE. in Japanese.
- T. Watanabe, M. Tazumi, T. Kiyohara, and M. Deguchi. Logic Verification
of High Performance Processor MN10400 Based on TRON Specification
for Real Memory System. IEICE SIG Report, FTS 90-3 (Apr. 1990),
IEICE. in Japanese.
- T. Watanabe, M. Tazumi, T. Kiyohara, and M. Deguchi. Logic Verification
of High Performance Processor MN10400 Based on TRON Specification
for Real Memory System. IEICE SIG Report, FTS 90-3, VLD 90-3 (1990),
IEICE.
- A. Yamada, H. Nakagawa, M. Hata, M. Satoh, K. Nishida, and T.
Hiraki. The Design Method of High Speed Cache Controller/Memory(CCM)
for the Gmicro Family Microprocessors. In TRON Project 1990 (1990),
Springer-Verlag, pp. 249-260.
- T. Yoshida, M. Matsuo, T. Ueda, and Y. Saito. A Strategy for
Avoiding Pipeline Interlock Delays in a Microprocessor. In Proceedings
of the 1990 International Conference on Computer Design: VLSI
in Computers and Processors (ICCD '90) (Cambridge, Massachusetts,
Sep. 1990), pp. 14-19.
- K. Yoshioka. TOBUS Outline and Its Feature. Proceedings of TRON
Technical Workshop, Vol. 3, No. 1 (Jun. 1990), pp. 47-64. in Japanese.
- A. Kabemoto, and H. Yoshida. The Architecture of the Sure System
2000 Communications Processor. IEEE Micro, Vol. 11, No. 4 (Aug.
1991), pp. 28-31, 73-78.
- M. Kainaga, K. Yamada, and H. Inayoshi. Analysis of SPEC Benchmark
Programs. In Proceedings of the Eighth TRON Project Symposium
(Nov. 1991), IEEE Computer Society Press, pp. 208-215.
- M. Kainaga, K. Yamada, and H. Chaki. CISC, Optimizing Compiler
and Super Scalar. Proceedings of TRON Technical Workshop, Vol.
3, No. 3 (1991), pp. 55-73. in Japanese.
- S. Kinoshita, and Y. Mori. Development of a Single-board Computer
System with TRON Specification Chip O32. Proceedings of TRON Technical
Workshop, Vol. 4, No. 1 (Jul. 1991), pp. 53-62. in Japanese.
- Y. Kittaka, T. Nasu, N. Kobayashi, and K. Saitoh. Development
of M32/100 Application System. Proceedings of TRON Technical Workshop,
Vol. 3, No. 3 (1991), pp. 43-54. in Japanese.
- H. Neugass, G. Espin, H. Nunoe, R. Thomas, and D. Wilner. VxWorks:
An Interactive Development Environment and Real-Time Kernel for
Gmicro. In Proceedings of the Eighth TRON Project Symposium (Nov.
1991), IEEE Computer Society Press, pp. 196-207.
- Y. Saito, H. Yoshida, H. Takada, and K. Sakamura. Godzilla's
Guide to Developing a Programming Environment for a New CPU. In
Proceedings of the 32th Programming Symposium (Tokyo, Jan. 1991),
IPSJ, pp. 131-142. in Japanese.
- Y. Shibata, M. Okazaki, M. Asai, and N. Kanazawa. Development
of TOXBUS-Based BUS Interface LSI. In Proceedings of the Spring
National Convention of IEICE (Mar. 1991), IEICE.
- M. Tazumi. The Method for Implementing the Microprogram-Simulator.
IPSJ SIG Notes on Computer Architecture, 87-6 (Mar. 1991), IPSJ.
in Japanese.
- O. Tomisawa. Recent Advances in TRON-Spec. Chips. In Proceedings
of the Eighth TRON Project Symposium (Nov. 1991), IEEE Computer
Society Press, pp. 178-184.
- K. Yamada, M. Kainaga, H. Yajima, Y. Tawara, and S. Kawanoue.
C Compiler Optimization for Gmicro. In Proceedings of the 43rd
National Convention of IPSJ (Oct. 1991), IPSJ, pp. 5.203-5.204.
- T. Yoshiba, T. Shimizu, S. Mizugaki, and J. Hinata. The Gmicro/100
32-bit Microprocessor. IEEE Micro, Vol. 11, No. 4 (Aug. 1991),
pp. 20-23, 62-72.
- H. Yoshida, Y. Saitoh, H. Takada, and K. Sakamura. A Study on
the Register Passing of Parameters on the TRON Specification Chip.
Proceedings of TRON Technical Workshop, Vol. 3, No. 3 (1991),
pp. 29-42. in Japanese.
- T. Yoshida, M. Matsuo, and S. Iwata. The Approach to Multiple
Instruction Execution in the Gmicro/400 Processor. In Proceedings
of the Eighth TRON Project Symposium (Nov. 1991), IEEE Computer
Society Press, pp. 185-195.
- S. Hayashida, and K. Tamaru. Optimizing Method of C Compiler
for TRON Architecture. In Proceedings of the Ninth TRON Project
Symposium (Dec. 1992), IEEE Computer Society Press, pp. 70-76.
- K. Hirano. A M32/100 Application to the X-Terminal. Proceedings
of TRON Technical Workshop, Vol. 4, No. 3 (Mar. 1992), pp. 13-23.
in Japanese.
- H. Iino, H. Takahashi, T. Sukemura, M. Kimura, K. Fujita, and
S. Mori. A 289MFLOPS Single-Chip Supercomputer. In 1992 IEEE International
Solid-State Circuits Conference Digest of Technical Papers (Feb.
1992), IEEE Computer Society Press, pp. 112-113.
- S. Inoue, S. Matsui, and M. Suzuki. TRON-specification CHIP
Compatibility Validation. In Proceedings of the Ninth TRON Project
Symposium (Dec. 1992), IEEE Computer Society Press, pp. 47-55.
- Y. Kashiwagi, Y. Tawara, H. Chaki, K. Yamada, Y. Kainaga, and
T. Isobe. An Optimizing C Compiler for the Gmicro/500 Microprocessor.
In Proceedings of the Ninth TRON Project Symposium (Dec. 1992),
IEEE Computer Society Press, pp. 63-69.
- S. Matsui, M. Yamamoto, I. Kawasaki, S. Narita, F. Arakawa,
K. Uchiyama, and K. Hashimoto. Gmicro/500 Microprocessor: Pipeline
Structure of Superscalar Architecture. In Proceedings of the Ninth
TRON Project Symposium (Dec. 1992), IEEE Computer Society Press,
pp. 56-62.
- K. Matsunami, T. Yamana, and H. Ito. Optimizing C Compiler for
the TRON Architecture. In Proceedings of the Ninth TRON Project
Symposium (Dec. 1992), IEEE Computer Society Press, pp. 77-87.
- K. Okada, and T. Komachiya. TRON-Specification Serial Bus. Proceedings
of TRON Technical Workshop, Vol. 4, No. 3 (Mar. 1992), pp. 1-11.
in Japanese.
- T. Ueda, H. Kondo, T. Yoshida, and T. Miyake. Evaluation of
the Microprocessor M32/100-boosted Performance by Onchip Cache
in Xbench Program. In Proceedings of the Workshop on Computer
Systems; Integrated Circuits and Devices (Oct. 1992), Vol. 92,
IPSJ, pp. 9-16. in Japanese.
- H. Yoshida. Data Profiler for Code Optimizations. Master's thesis,
Graduate School of University of Tokyo, Division of Science, Feb.
1992.
- M. Awaga, and H. Takahashi. The microVP 64-Bit Vector Coprocessor:
A New Implementation of High-Performance Numerical Computation.
IEEE Micro, Vol. 13, No. 5 (Oct. 1993), pp. 24-36.
- H. Goto, and Y. Nozuyama. Design of 32-bit TX2 Microprocessor
Based on TRON Specification. In Proceedings of the Tenth TRON
Project Symposium (Dec. 1993), IEEE Computer Society Press, pp.
68-77.
- T. Inoue. TRON-specification Chip Compatibility Validation of
TX1. Proceedings of TRON Technical Workshop, Vol. 5, No. 2 (Mar.
1993), pp. 67-73. in Japanese.
- A. Matsui. Gmicro/500 Microprocessor Application System: Performance
Evaluation of Graphic Primitives. In Proceedings of the Tenth
TRON Project Symposium (Dec. 1993), IEEE Computer Society Press,
pp. 61-67.
- S. Mori, H. Kishigami, I. Kawasaki, and Y. Saitoh. Future Technology
Directions in TRON-Specification Chips. In Proceedings of the
Tenth TRON Project Symposium (Dec. 1993), IEEE Computer Society
Press, p. 79.
- M. Yamamoto, and I. Kawasaki. Performance Evaluation of Gmicro/500
Microprocessor for CTRON based kernel. In Proceedings of the Tenth
TRON Project Symposium (Dec. 1993), IEEE Computer Society Press,
pp. 52-60.
- H. Hayashi, and E. Masuda. Accelerating Multiplication and Division
in High-Speed Microprocessor Systems. Proceedings of TRON Technical
Workshop, Vol. 6, No. 1 (Mar. 1994), pp. 37-45. in Japanese.
- J. Korematsu, T. Ueda, M. Matsuo, K. Tani, N. Okumura, K. Ishimi,
T. Yoshida, Y. Saito, and J. Hinata. A 32-bit Superscalar Microprocessor
Gmicro/400 for Embedded Systems. In Proceedings of the Eleventh
TRON Project Symposium (Dec. 1994), IEEE Computer Society Press,
pp. 115-121.
- S. Mori. The Present and Future of the TRON-specification CHIP
- Promoting Open Architecture and Standardization -. Journal of
Information Processing Society of Japan, Vol. 35, No. 10 (Oct.
1994). in Japanese.
- Y. Nozuyama, H. Mitani, T. Fukumoto, T. Utsumi, and K. Hashimoto.
A 32-bit Microprocessor with Efficient Testable Designs, the TX2.
In Proceedings of the Eleventh TRON Project Symposium (Dec. 1994),
IEEE Computer Society Press, pp. 122-130.
- H. Shimbo, E. Masuda, and K. Okada. Quantitative Evaluation
of the Reliability Benefits of Maintenance Bus Implementation.
In Proceedings of the Eleventh TRON Project Symposium (Dec. 1994),
IEEE Computer Society Press, pp. 131-139.
- K. Tani, S. Kobayashi, M. Matsuo, Y. Saito, and J. Hinata. Hardware
Structure of 32-bit Microprocessor Gmicro/400. Proceedings of
TRON Technical Workshop, Vol. 6, No. 1 (Mar. 1994), pp. 37-45.
in Japanese.
- T. Usaka, Y. Sasaki, H. Takada, and K. Sakamura. A Software
Development Environment for TRON-Specification Chips. In Poster
Session Material of the Eleventh TRON Project Symposium (Dec.
1994), TRON Association.
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